In general, microelectromechanical systems (MEMS) are miniature devices combining both electrical and mechanical components that are typically fabricated with batch-processing techniques borrowed from integrated circuit (IC) manufacturing technology. See, for example, J. Bryzek et al., “Micromachines on the March”, IEEE Spectrum Mag., May 20, 1994. Examples of representative MEMS devices include: accelerometers; optical switches; gyroscopes; sensors and actuators. Integrated MEMS (IMEMS) generally combine IC's with MEMS devices on a substantially unitary substrate. In either case, MEMS and IMEMS devices are usually adapted to employ spatially active elements (i.e., gears, pivots, hinges, levers, slides, etc.) which typically must be free to move in order to function for their intended purpose.
Development of MEMS technology has generally been driven by ontological advancements in the commercial electronics industry along with increasing demand for sophisticated devices having reduced parts count, weight, form factors and power consumption while improving or otherwise maintaining overall device performance. In particular, application of MEMS technology to RF and microwave component design has met with considerable success in the areas of systems integration and the development of novel architectures directed to achieving many of these aims at relatively low fabrication cost.
With the potential to enable wide operational bandwidths and the reduction of interconnect losses to near negligible levels, MEMS technology has been projected to provided on-chip switches with virtually zero standby power consumption and nano-Joule switching with low voltage actuation. Other representative applications include the production of high stability (e.g., “quartz-like”) oscillators and high performance miniaturized components, such as, for example, capacitors, inductors, filters and the like.
Representative technologies employing MEMS devices in RF applications include, for example: mobile phone and wireless communications; wireless Internet access; wireless data devices, such as various Bluetooth® compliant peripherals; and location services (i.e., GPS). For a general discussion of RF MEMS technology, see, for example, Elliot R. Brown, “RF-MEMS Switches for Reconfigurable Integrated Circuits”, IEEE 0018-9480/98, 1998; and Sergio P. Pacheco et al., “Design of Low Actuation Voltage RF MEMS Switch”, IEEE 0-7803-5687-X/00, 2000.
There are several MEMS fabrication techniques currently in commercial use, including, for example, bulk micromachining, surface micromachining, fusion bonding and LIGA (e.g., X-ray lithographic electroforming). In bulk micromachining, 3D structures are generally sculpted within the confines of a substrate by exploiting anisotropic etching rates of different atomic crystallographic planes in the substrate. Alternatively, structures may be formed by a process of fusion bonding, which generally involves building-up a structure by atomically bonding various substrates to one another. In surface micromachining, 3D structures are typically built-up by the addition and removal of a sequence of film layers to and from a substrate surface which are generally termed “structural” and “sacrificial” layers, respectively. The success of the surface micromachining approach usually is proportional to the ability to release or dissolve the sacrificial layers while preserving the integrity of the structural elements. In the LIGA process, relatively thick photoresists are exposed to X-rays in order to produce molds that are subsequently used to form high aspect ratio electroplated 3D structures. However, to date, the most widely used technique for RF MEMS manufacture has been surface micromachining.
In general, surface micromachining consists of the deposition and lithographic patterning of various films—usually on silicon substrates. Typically, the procedure involves making one or more “release” films over a specific region of the substrate wherein the films are suitably adapted for subsequent release of patterned structures therein to permit mechanical motion and/or actuation of the developed MEMS structural elements. This may be accomplished, for example, by depositing a “sacrificial” film below the released ones, which may be removed near the end of the process by selective etching. Various materials may be employed for the deposition of release and/or sacrificial layers, including, for example: metals (i.e., Au, Al, etc.); ceramics (SiO2, Si3N4, SiC, AIN, etc.) and plastics (photoresist, polymethyl methacrylate (PMMA), etc.). Depending on the process design specifications and the presence of other materials present in the film stack, the release and sacrificial layers may be deposited by evaporation, sputtering, electrodeposition or other methods well-known in the art.
More recent developments in surface micromachining methods have been realized with the application of dry etching techniques; particularly reactive-ion etching (RIE). By mixing reactive chemicals in a plasma stream and exposing a substrate with films deposited thereon, certain materials on the surface may be selectively etched at relatively high rates. For example, chlorine-bearing compounds in a high density plasma have been observed to yield nearly isotropic silicon etching with a selectivity of Si:SiO2 of better than 100:1.
On the other hand, low-pressure plasma etching (e.g., inductively coupled plasma (ICP)) generally permits bulk micromachining of mechanical structures directly in silicon, quartz or other substrates by selectively removal of substrate material. Low-pressure plasma etching is generally believed to be the most mature of the micromachining technologies and has been used for several years in the manufacture of a variety of sensors and actuators such as pressure sensors, accelerometers and ink-jet nozzles. The process also may include the steps of wet chemical etching and/or RIE to form released microstructures. With wet etching, the resulting structures generally depend on the directionality of the etch, which is usually a function of the crystallinity of the substrate as well as the etching chemistry. Accordingly, the spatial features of the resulting microstructures become a convolution of the etch-mask pattern with the etching directionality. Hence, the narrow deep microstructures generally desired in bulk micromachining are often difficult to achieve and better results may often be achieved with RIE techniques. One relatively common RIE bulk micromachining technique is known as single-crystal reactive etching and metalization (SCREAM), which has been used to make comparatively deep microstructures in silicon and GaAs. See, for example, K. A. Shaw et al., Sens. Actuators, 40, 1994; and Z. L. Zhang and N. C. MacDonald, J. Micromechanical Syst, 2, 66-72, 1993. The SCREAM process has generally demonstrated the capability to produce structures having aspect ratios up to 50 or more which span over lateral dimensions of up to about 5 mm.
As is generally well-known, good fabrication and packaging techniques are relatively important for the successful performance of conventional RF or microwave components. Generally speaking, this may be even more critical in the case of the fabrication and packaging of MEMS devices. Indeed, in addition to aiding with the reduction of unwanted resonances and electromagnetic (EM) interference and/or coupling, conventional MEMS packaging methods generally aim to prevent moisture and various particulate contaminants which may prevent or otherwise impede the movement of freestanding MEMS structures or otherwise may be responsible for other energy losses (i.e., acoustic, thermal, etc.). The two most commonly employed MEMS packaging techniques to date have been the “flip-chip” and the “self-packaging” methods. See, for example, David C. Miller et al., “Microrelay Packaging Technology using Flip-Chip Assembly”, The Thirteenth Annual International Conference on Micro Electromechanical Systems, 265-270, IEEE 0-7803-5273-4/00; and S. V Robertson et al., “Micromachined Self-packaged W-band Bandpass Filters”, IEEE MTT-S International Microwave Symposium Digest, 1543-1546, 3, 1995.
Conventional MEMS dies are typically fabricated with wirebond pads and utilize a variety of sealing mechanisms. For example, a cap may be provided with a cavity etched for receiving a micromachined device structure therein. The cap may be attached to the die by an adhesive. The die and cap may be assembled on, for example, a ceramic substrate where the bond pads of the die are wirebonded to bond pads of the ceramic. Thereafter, the ceramic assembly may then be encapsulated within a hermetic package.
As a result, conventional MEMS packaging systems and methods suffer from several problems. For example, wirebonds are generally fragile and susceptible to damage during mechanical assembly of the package. Additionally, if any of the microcomponents prove defective, the entire circuit lot must generally be discarded. Moreover, MEMS structures typically contain various metal elements on their surfaces which usually may not be passivated through conventional processes; however, most device packages generally must still be hermetically sealed. Accordingly, previous attempts at packaging MEMS devices have met with substantial difficulties in producing reliable electrical connections and/or hermetic seals capable of withstanding manufacturing process stress while maintaining or otherwise reducing production costs.
For many conventionally produced MEMS components, the steps of packaging and testing may account for between about 70-95% of the total fabrication cost. Existing semiconductor packaging methods, although generally less expensive, have not yet been adequately adapted for successfully extensible application to MEMS fabrication with commercially acceptable yields and/or reliability. Despite the efforts of prior art designs, none have yet realized reliable wafer level packaging of MEMS device arrays that are readily manufacturable at low cost. Accordingly, a representative limitation of the prior art concerns inter alia the effective and efficient wafer level packaging of MEMS devices prior to wafer dicing and device singulation.